DATASHEET: NEOCORTEX-1 PULSED NEURAL CO- PROCESSOR 140 Synapses x 10 Neurons vWISP Pty. Ltd.
The vWISP NeoCortex-1 is a research version a new type of coprocessor. Like signal processors that appeared in the 1980’s, the NeoCortex-1 is set to revolutionize the way neural networks are built. The device is stackable and contains 140 dynamic synapses and 10 neural processing junctions. The operation of the device is very similar to the way a biological neuron operates; when the input is pulsed the membrane potential is increased or decreased in a ‘leaky integrator’. In the biological model the membrane potential increases as vesicles are passed into the synaptic cleft. Over time, the Ca+ value increments to a preset maximum value while the integrator value (PSP or membrane potential) declines, e.g. charge ‘leaks’ out of the integrator. The timing of input signals to each other, the time elapsed since the last input pulse, soma sensitivity and the axon delay are all factors of the transfer function. Later commercial devices will contain up to 15,000 neurons and 210,000 synapses and are organized in rows and columns.
PROCESSOR REGISTERS
The vWISP Cortex-1 component contains 140 dynamic synapses and 10 neuron junctions. Each synapse can be inhibiting or excitatory, depending on the pattern written to the Inhibit mask registers. A ‘1’ in the Inhibit mask sets the synapse to be excitatory. 14 bits are used in each Inhibit Mask, representing synapses 0-13. The top two bits are used for future enhancement. The timing of the axon output depends on the soma sensitivity and the axon delay registers. Axon delay = Tclk * DELAY
Tclk is the clock period and DELAY is the contents of the Axon Delay register. If the axon delay is set to a low value and the soma sensitivity is set to an appropriate value then the bursting behavior shown in the diagram of Page 2 will be observed.
Sequence of events At an excitatory synapse, when an input pulse occurs, the then current Ca+ register value is added to the Membrane Potential of the Soma. The Soma Membrane Potential is the sum of all synapses PSP, including the negative values that are generated by Inhibitory synapses. The Ca+ value is cleared immediately after an input pulse and starts increasing to the value in the Ca+ register. The Membrane Potential is an internal register that can not be read. The Membrane potential decreases at half the Tclk rate. Whenever the Membrane Potential (PSP) reaches or exceeds the value contained in the Sensitivity register an output event is triggered. The output event repeats for as long as the summed PSP is higher or equal to the Sensitivity value. The PSP and Sensitivity values are 2’s complement: 0 to 7Fh are positive values, 80h to FFh are negative whereby 80h is equivalent to -127. The CLK input is fast compared to the input pulses, typical by a factor 2^8 for an 8 bit system. The decline in Membrane Potential is a function of the CLK signal. The Membrane Potential will decline to zero in Tdecline = 2 * Membrane potential * Tclk
The current Ca+ value (available Ca+ in the synapse) is:
max Ca+ = ∑∆t I Clk=1
For example, assuming that only one synapse is pulsed, the clock period is 100 µS and the maximum Ca+ value is set to 14h (20d). The actual Ca+ value will reach the maximum value after 0.0001 * 20 = 2 mS. During the same time the Membrane potential will have declined by 2mS/(2*100µS) = 10d or 0Ah unless the neuron was at equilibrium. If an input pulse is received at that time, the value 14h is added to 0Ah and the membrane potential is 01Eh No trigger event occurs if the soma sensitivity is set to 43h. After another 2 mS the Membrane potential has declined to 14h and 14h is added when a pulse occurs at this time. The membrane voltage is now 28h. After 2 mS the membrane voltage is 1Eh and 14h is added, resulting in 32h. Next, the membrane voltage declines to 28h plus 14h results in 3Ch. At the next input pulse a trigger event occurs; 3C declines to 32h plus 14h = 46h. This declines to 43h in 3 * (2 * 100µS). An output pulse will be generated, it’s timing depending on the Axon delay value. The axon delay is DELAY * Tclk. Therefore if delay >3 only a single pulse will be generated in this case. The sequence of five input pulses, 2 mS apart has resulted in the generation of a single output pulse. Output pulses are one clock period wide. The interval between pulses is (Delay * Tclk).
PIN DESCRIPTIONS
Clear Synapses when 0 (not registers) _CLEAR
TYPICAL APPLICATION
Copyright 2004 by the Genetics Society of AmericaDOI: 10.1534/genetics.104.026716 Virulence, Multiple Infections and Regulation of Symbiotic Population in the Wolbachia -Asobara tabida Symbiosis Laurence Mouton,*,1 Franck Dedeine,*,† He´le`ne Henri,* Michel Boule´treau,* Ne´rina Profizi‡ and Fabrice Vavre* * Laboratoire de Biome´trie et Biologie Evolutive (UMR-CNRS 5558)
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DATASHEET: NEOCORTEX-1 PULSED NEURAL CO-
PROCESSOR REGISTERS 
REGISTER NAME 
Axon delay = Tclk * DELAY 
For example, assuming that only one synapse is pulsed, the clock period is 100 µS and the maximum Ca+ value is set to 14h (20d). The actual Ca+ value will reach the maximum value after 0.0001 * 20 = 2 mS. During the same time the Membrane potential will have declined by 2mS/(2*100µS) = 10d or 0Ah unless the neuron was at equilibrium. If an input pulse is received at that time, the value 14h is added to 0Ah and the membrane potential is 01Eh No trigger event occurs if the soma sensitivity is set to 43h. After another 2 mS the Membrane potential has declined to 14h and 14h is added when a pulse occurs at this time. The membrane voltage is now 28h. After 2 mS the membrane voltage is 1Eh and 14h is added, resulting in 32h. Next, the membrane voltage declines to 28h plus 14h results in 3Ch. At the next input pulse a trigger event occurs; 3C declines to 32h plus 14h = 46h. This declines to 43h in 3 * (2 * 100µS). An output pulse will be generated, it’s timing depending on the Axon delay value. The axon delay is DELAY * Tclk. Therefore if delay >3 only a single pulse will be generated in this case. The sequence of five input pulses, 2 mS apart has resulted in the generation of a single output pulse. Output pulses are one clock period wide. The interval between pulses is (Delay * Tclk).
PIN DESCRIPTIONS 
TYPICAL APPLICATION